Emitter turn-off thyristors (ETO)

ABSTRACT

A family of emitter controlled thyristors employ plurality of control schemes for turning the thyristor an and off. In a first embodiment of the present invention a family of thyristors are disclosed all of which comprise a pair of MOS transistors, the first of which is connected in series with the thyristor and a second which provides a negative feedback to the thyristor gate. A negative voltage applied to the gate of the first MOS transistor causes the thyristor to turn on to conduct high currents. A zero to positive voltage applied to the first MOS gate causes the thyristor to turn off. The negative feedback insures that the thyristor only operates at its breakover boundaries of the latching condition with the NPN transistor portion of the thyristor operating in the active region. Under this condition, the anode voltage V A  continues to increase without significant anode current increase. Emitter turn-off (ETO) thyristor fabrication packages are also disclosed having packaged semiconductor devices controlling the thyristor.

This application is the national phase of PCT International ApplicationNo. PCT/US98/20594 filed on Sep. 30, 1998 under 35 U.S.C. § 371. Thisapplication also claims priority of provisional Application No.60/060,557 filed in United States on Sep. 30, 1997.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a novel family of thyristorsand, more particularly, to a family of low cost metal oxidesemiconductor (MOS) emitter turn-off thyristors.

2. Description of the Prior Art

Thyristors, sometimes referred to as silicon controlled rectifiers, arefour layer pnpn devices comprising an anode, a cathode, and a gateterminal. Thyristors are designed to carry very high currents with verylittle voltage drop. For example, at currents of up to 500 A, thevoltage drop across the anode and cathode terminals typically does notexceed 2 V. This makes thyristors ideal for power electronics switchingapplications such as converting one power form to another, such as, forexample dc-ac or dc-dc.

Standard thyristors are turned on by applying a short current pulseacross the cathode and gate terminals. Once the device is turned on,high currents may flow between the anode and cathode. Unfortunately, thegate can only be used to turn the device on, it cannot be used to turnthe device off. Turn-off is accomplished by applying a reverse voltageacross the anode and the cathode. Several variations of the standardthyristor have been developed to facilitate the turn-off operation suchas, for example, gate turn-off thyristors (GTO) and metal-oxidesemiconductor (MOS)-controlled thyristors (MCTs).

Gate turn-off thyristors (GTO) have been developed which can turn thedevice off by applying a reverse gate pulse to bypass carriers directlyto the gate circuit. However, GTO's are known to have a poor turn offcurrent gain. For example, a GTO having a 2000 A peak current mayrequire up to 500 A of reverse gate current.

The MOS-controlled thyristor (MCT) has been around for about a decadeand is basically a thyristor including two built in MOS transistors, oneto turn the thyristor on, and one to turn it off. The gates of the twoMOS transistors are tied together. A relatively low negative voltagepulse (i.e., −7 V) to the gates turn the thyristor on, and a positivepulse (i.e., 14 V) to the gates turn the thyristor off. Hence, the MCThas the advantage of being able to be driven directly by logic gates.However, MCTs are typically expensive to fabricate and very difficult toscale to high voltage (e.g., >2 KV) and high current (e.g., >100 A).

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide animproved family of emitter turn-off (ETO) thyristors which are suitablefor operation in high frequency and which are inexpensive to fabricate.

It is yet another object of the present invention to provide an improvedfamily of emitter turn-off thyristor (ETO) to replace the GTO, and animproved family of emitter-controlled thyristor (ECT) to replace MCT.ETO and ECT are based on the same operation principle of emittercontrol, but ETO is a hybrid device hence is inexpensive in fabrication,while the ECT is a monolithic device that requires standard power devicefabrication process.

Disclosed herein is a family of emitter controlled thyristors (ECT) andemitter turn-off thyristors ETO employing a plurality of control schemesfor turning the thyristor on and off. In a first embodiment of thepresent invention a family of thyristors are disclosed all of whichcomprise a pair of MOS transistors, the first of which is connected inseries with the thyristor (hence after called emitter switch, or Q_(E)or Q1) and a second which provides a connection from the thyristor gateto the cathode or ground (hence after called gate switch or Q_(G) orQ2). A third optional MOSFET (hence after called Q_(ON) or Q3) is usedto provide the turn-on mechanism for the thyristor. Depending on whethera n-channel or p-channel device is used for Q_(E). A negative voltageapplied to the gate of the first MOS causes the thyristor to turn on toconduct high currents. A zero to positive voltage applied to the firstMOS gate causes the thyristor to turn off. A negative feedback mechanismalso exist between the Q_(E) and Q_(G) at high currents that causes theECT to operate at its breakover boundaries of the latching conditionwith the NPN transistor portion of the thyristor operating in the activeregion. Under this condition, the anode voltage V_(A) continues toincrease without significant anode current increase. ETO devicesdisclosed here also use at least two switches Q_(G) and Q_(E) to controlthe current. They also have the negative feedback mechanism that causesthe current to saturate at high currents. In particular, ETO fabricationpackages are also disclosed having packaged semiconductor devicescontrolling the thyristor.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, aspects and advantages will be betterunderstood from the following detailed description of a preferredembodiment of the invention with reference to the drawings, in which:

FIGS. 1A and 1B are a cross sectional view and an equivalent circuitdiagram, respectively, of an emitter controlled thyristor according to afirst embodiment of the invention;

FIGS. 1C and 1D are a cross sectional view and an equivalent circuitdiagram, respectively, of an emitter controlled thyristor similar tothat of FIGS. 1A–B having an additional NMOS transistor connected acrossthe thyristor for device turn-on;

FIGS. 2A and 2B are a cross-sectional view of the ECT with a turn-oncell (ECT-OC) and its circuit equivalent, respectively;

FIGS. 3A and 3B are a cross-sectional view of a lateral emittercontrolled thyristor (LECT), respectively;

FIGS. 4A and 4B are a cross-sectional view of a lateral NMOS emittercontrolled thyristor (LNECT) controlled thyristor and its circuitequivalent, respectively;

FIGS. 5A and 5B are a cross-sectional view of a lateral emittercontrolled thyristor (LECT) and its circuit equivalent, respectively;

FIGS. 6A and 6B are a cross-sectional view of an alternate embodiment ofthe ECT shown in FIGS. 1A–B with a metal connection and its circuitequivalent, respectively;

FIGS. 7A and 7B are a cross-sectional view of a single gate NMOS emittercontrolled thyristor (SNECT) and its circuit equivalent, respectively;

FIGS. 8A and 8B are a cross-sectional view of a single gate emittercontrolled thyristor (SECT) and its circuit equivalent;

FIGS. 9A and 9B are a cross-sectional view of an emitter turn offthyristor (ETO) and its circuit equivalent, respectively, according to asecond embodiment of the present invention;

FIGS. 10A and 10B are a cross-sectional view of an alternate emitterturn off thyristor (ETO) and its equivalent circuit;

FIGS. 11A and 11B are a cross-sectional view of an alternate emitterturn off thyristor (ETO) and its circuit equivalent, respectively;

FIGS. 12A and 12B are a cross-sectional view of an alternate emitterturn off thyristor (ETO) and its equivalent circuit, respectively;

FIGS. 13A and 13B are a cross-sectional view of an alternate emitterturn off thyristor (ETO) and its circuit equivalent, respectively;

FIGS. 14A and 14B are a cross-sectional view of an alternate emitterturn off thyristor (ETO) and its equivalent circuit, respectively;

FIGS. 15A and 15B are a cross-sectional view of a package that attachesto a MOSFET die on a single emitter finger of the GTO and its equivalentcircuit, respectively, similar to that shown in FIG. 9;

FIGS. 16A and 16B are a cross-sectional view of a package that attachesto a MOSFET die on multiple emitter fingers of the GTO and equivalentcircuit, respectively, similar to that shown in FIG. 9 but havingmultiple emitter fingers in the active area;

FIG. 17A is cross sectional view of an ETO packaged by connections Q_(G)and Q_(E) externally;

FIGS. 17B–D are an equivalent circuit, top, and perspective view,respectively, of the ETO fabrication package shown in FIG. 17A.

FIGS. 17E–F voltage-current turn-on and turn-off timing diagrams,respectively, for the ETO package shown in FIG. 17A;

FIG. 18 is a schematic showing connection of the ETO implemented inFIGS. 17A–D that provides a three terminal solution wherein a feedbacknetwork is implemented between the gate of Q_(E) and the drain of Q_(E);and

FIG. 19 is a schematic showing a ETO connection as implemented in FIGS.17A–D that provides a separate drive signal to Q_(E) and Q_(G), and acapacitor C in parallel with Q_(G).

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION

Referring now to the drawings, and more particularly to FIGS. 1A and 1B,there is shown a cross-sectional view of the emitter controlledthyristor (ECT) and its equivalent circuit, respectively. The ECT has afour-layer PNPN thyristor structure 2, in series with a P channel MOSFET(PMOS1) 10 integrated on the top N layer. In FIG. 1B the PNPN thyristoris shown as a PNP bipolar transistor 6 and NPN bipolar transistor 8. AFloating Ohmic Contact (FOC) 12 shorting the N emitter 14 and the P+region 16 which acts as the source of the PMOS1 10. The FOC 12 providesthe bridge for transferring emitter electron currents of the upper NPNtransistor into hole currents, which then flow through the PMOS1 10channel and into the cathode contact 18. A second PMOSFET (PMOS2) 20 isformed at the other side of the cathode contact with the upper P base 22acting as the source. The PMOS2 does not have a separate control gate,instead, its gate 24 is tied to the cathode contact 18.

During the forward current conduction, a large negative gate voltage isapplied to the main gate 26, the ECT current flows vertically along thePNPN thyristor structure, and then laterally flows through the seriesPMOS1 and into the cathode 18. The ECT's forward voltage drop istherefore that of a thyristor plus that of the PMOS1 10.

With the increase of the current, the voltage of the FOC 12, V_(FOC),will increase due to the channel resistance of the PMOS1 10. WhenV_(FOC)>−V_(T2), where V_(T2)<0 is the threshold voltage of the PMOS220, the PMOS2 20 turns “on”, and hole currents will be diverted from theupper base through the PMOS2 20 into the cathode 18. The turn-on of thePMOS2 20 will reduce the upper NPN transistor's 6 current gain. If thereduction of the upper NPN transistor 6 current gain, Δα_(npn), cannotbe compensated by an increase of the lower PNP transistor 8 currentgain, Δα_(npn), so thatα_(npn0)+α_(pnp0)−Δα_(pnp)≦1  (1)then the ECT will come out of latching state. If this happens, thecurrent flowing through the PMOS1 10 will tend to decrease, and so willthe V_(FOC). A reduced V_(FOC) means a reduction of the diverted currentthrough the PMOS2 20 and the decrease of the Δα_(npn:) hence, the ECTenters latching again. Such negative feedback mechanism, therefore,leads to the fact that the main thyristor 2 can only operate at thebreakover boundaries of the latching condition with the NPN transistor 6operating in the active region. Under this condition, the anode voltageV_(A) continues to increase without significant anode current increase,and the increased anode voltage is supported by the main junction J3.The lower PNP transistor 8 (also operating in the active region)supplies base current for the upper NPN transistor 6, and the saturationcurrent is the holding current of the thyristor with both PMOS1 10 andPMOS2 20 conducting. This phenomena is called high voltage currentsaturation or forward bias safe operation area (FBSOA). At very highvoltages, the increase of α_(pnp) will compensate α_(npn), and the ECTwill tend to latch again until equation (1) is violated. The violationpoint can be considered to correspond to the ECT's FBSOA boundary point.

The ECT can be turned-off by increasing the gate electrode voltage tozero or positive value in PMOS1 10, which interrupts the main currentflow path. All currents are then forced to divert to the cathode by thePMOS2 20. Both emitter switch (PMOS1) and emitter short (PMOS2) are usedin the turn-off of the ETC., and unlike in the EST, no parasiticthyristor limits the reverse bias safe operation area (RBSOA) of theECT.

FIGS. 1C and 1D show an ECT and its schematic equivalent having MOSturn-on, and an emitter switch for MOS turn-off. As shown in FIG. 1D,the thyristor of FIG. 1C–D is similar to that shown in FIGS. 1A–B withthe addition of an NMOS transistor 70. The additional NMOS 70 isdesigned to be a depletion MOSFET. The gate of it is also tied toground. The leakage current of this MOSFET will turn-on the ECT when anegative gate voltage is applied to the main control gate, 26.

Referring now to FIG. 2A there is shown a cross-sectional view of theECT with a novel turn-on cell (ECT-OC) 30 and FIG. 2B shows its circuitequivalent. The circuit is similar to the one shown in FIG. 1 with theaddition of an avalanche diode 30 connected between the gate 48 of thefirst PMOS and the thyristor. The ECT-OC has a 4-layer PNPN thyristorstructure 2 in series with a P channel MOSFET (PMOS1) 32 integrated onthe top N layer 34. A Floating Ohmic Contact (FOC) 36 shorting a P+region 38 and the N emitter acts as the source of the PMOS1 32. The FOC36 provides the bridge for transferring emitter electron currents of theupper NPN transistor 40 into hole currents, which then flow through thePMOS1 32 channel and into the cathode contact 42. A second PMOSFET(PMOS2) 44 is formed at the other side of the cathode contact 42 withthe upper P base 46 acting as the source. The PMOS2 44 does not have aseparate control gate, instead, its gate is tied to the cathode contact42. A P+-N diode 46 forms the turn-on cell located in the top N region,and its P+ anode is tied to the gate electrode of the ECT-OC.

When a positive bias is applied to the anode and a negative gate voltageis applied to the gate electrode 48, the avalanche breakdown will beappeared at the P+-N junction of the turn-on cell 30. Electrons createdby the avalanche breakdown will injected into the thyristor and triggerthe thyristor into the latching state. The ECT-OC current flowsvertically along the P+-N-P-N thyristor structure, and then laterallyflows through the series PMOS1 32 and into the cathode 42. The ECT-OC'sforward voltage drop is therefore that of a thyristor plus that of thePMOS1 32. With the increase of the current, the voltage of the FOC 36,V_(FOC), will increase due to the channel resistance of the PMOS1 32.When V_(FOC)>−V_(T2), where V_(T2)<0 is the threshold voltage of thePMOS2 44, the PMOS2 44 turns ‘on’, and hole currents will be divertedfrom the upper base through the PMOS2 44 into the cathode 42. Theturn-on of the PMOS2 44 will reduce the upper NPN transistor's currentgain. If the reduction of the upper NPN transistor 40 current gain,Δα_(npn), cannot be compensated by an increase of the lower PNP 50transistor current gain, Δα_(pnp), so thatα_(npn0)+α_(pnp0)−Δα_(npn)+Δα_(pnp)≦1  (2)then the ECT-OC will come out of latching state. If this happens, thecurrent flowing through the PMOS1 32 will tend to decrease, and so willthe V_(FOC). A reduced V_(FOC) means a reduction of the diverted currentthrough the PMOS2 44 and the decrease of the Δα_(npn), hence the ECT-OCenters latching again. Such negative feedback mechanism, therefore,leads to the fact that the main thyristor can only operate at thebreakover boundaries of the latching condition with the NPN transistor40 operating in the active region. Under this condition, the anodevoltage V_(A) continues to increase without significant anode currentincrease, and the increased anode voltage is supported by the mainjunction J3. The lower PNP transistor 50 (also operating in the activeregion) supplies base current for the upper NPN transistor 40, and thesaturation current is the holding current of the thyristor with bothPMOS1 32 and PMOS2 44 conducting. At very high voltages, the increase ofΔα_(pnp) will compensate Δα_(npn) and the ECT-OC will tend to latchagain until equation (2) is violated. The violation point can beconsidered to correspond to the ECT-OC's FBSOA boundary point.

The ECT-OC can be turned-off by increasing the gate electrode 48 voltageto zero or positive value in the PMOS1 32, which interrupts the maincurrent flow path. All currents are then forced to divert to the cathodeby the PMOS2 44. Both emitter switch (PMOS1) 32 and emitter short(PMOS2) 44 are used in the turn-off of the ECT, and unlike in the EST,no parasitic thyristor limits the RBSOA of the ECT-OC.

FIGS. 3A–B show lateral emitter controlled thyristor (LECT)cross-section and its equivalent circuit diagram, respectively on asilicon oxide SiO substrate. The LECT has a lateral 4-layer P⁺-N-P-N⁺thyristor structure 2 in series with a P channel MOSFET (PMOS1) 60integrated on the surface of the N layer through a Floating OhmicContact (FOC) metal strap 62. The FOC 62 connects the upper N⁺ emitter64 of the PNPN thyristor and the P⁺ source region 66 of the PMOS1 60.The FOC 62 provides the bridge for transferring emitter electroncurrents of the NPN transistor into hole currents, which then flowthrough the PMOS1 60 channel and into the cathode contact 68. AnN-channel depletion mode MOSFET (NMOS) 70 is also integrated at thesurface of the LECT which acts as the turn-On MOSFET. A second PMOSFET(PMCS2) 72 is formed between the P base 74 and the P⁺ drain 76 of thePMOS1 60 with the P base 74 acting as its source. The NMOS 70 and thePMOS2 72 share the same gate 78, and the gate is directly tied to thecathode contact 68, hence, the LECT is a three-terminal device.

When a positive bias is applied to the anode 80 and a negative gatevoltage is applied to the gate electrode 78, the depletion mode NMOS 70will inject electrons into the n-drift region of the thyristor andtrigger the thyristor into the latching state. The latching currentflows into the N⁺ emitter 64 of the thyristor and then flows into thecathode 68 through the FOC metal strap 62 and the series PMOS1 60. TheLECT's forward voltage drop is therefore that of a thyristor plus thatof the PMOS1 60. With the increase of the current, the voltage at theFOC metal strap 62, V_(m), will increase, the PMOS2 72 will be turned‘on’ and hole currents will be diverted from the p base through thePMOS2 72 into the cathode 68. Consequently, the turn-on of the PMOS2 72will reduce the NPN transistor's current gain. If the reduction of theNPN transistor current gain, Δα_(npn) cannot be compensated by anincrease of the PNP transistor current gain, Δα_(pnp) so thatα_(npn0)+α_(pnp0)−Δα_(npn)+Δα_(pnp) ≦1  (3)then the LECT will come out of latching state. If this happens, thecurrent flowing through the PMOS2 72 will tend to decrease, and so willthe V_(m). A reduced V_(m) means a reduction of the diverted currentthrough the PMOS2 72 and the decrease of the Δα_(npn) hence the LECTenters latching again. Such negative feedback mechanism, therefore,leads to the fact that the main thyristor can only operate at thebreakover boundaries of the latching condition with the NPN transistoroperating in the active region. Under this condition, the anode voltageV_(A) continues to increase without significant anode current increase,and the increased anode voltage is supported by the main junction J2.and the LECT has a high voltage current saturation capability.

The LECT can be turned-off by increasing the gate electrode 78 voltageto zero or positive to turned ‘off’ the PMOS1 60, which interrupts themain current flow path, and all currents are then forced to divert tothe cathode 68 by the PMOS2 72. Moreover, both emitter switch andemitter short are used in the turn-off of the LECT, no parasiticthyristor limits the Reverse Bias SCA (RBSCA) of the LECT.

Referring now to FIGS. 4A–B, there is shown a cross-sectional view ofanother lateral emitter controlled thyristor (LNECT) on the siliconoxide (SiO) substrate 90 and its equivalent circuit, respectively. TheLNECT has a lateral 4-layer P⁺-N-P-N⁺ thyristor 2 structure in serieswith a N channel MOSFET (NMOS1) integrated on the surface of the P wellthrough a Floating Ohmic Contact (FOC) metal strap. The FOC connects theupper N⁺ emitter of the PNPN thyristor and the N⁺ drain region of theNMOS1. An N-channel depletion mode MOSFET (NMOS2) is also integrated atthe surface of the LNECT which acts as the turn-on MOSFET. A P-channelMOSFET (PMOS) is formed between the P base and the P well with the Pbase acting as its source. The cathode shorts the N⁺ source of the NMOS192 and the P well 94. The gate electrode 96 of the NMOS2 98 and the PMOSis directly tied to the cathode contact 102; hence, the LNECT is athree-terminal device.

When a positive bias is applied to the anode and the gate electrode 96,the depletion mode NMOS2 98 will inject electrons into the N-driftregion of the thyristor and trigger the thyristor into the latchingstate. The latching current flows into the N⁺ emitter of the thyristorand then flows into the cathode 102 through the FOC metal strap 104 andthe series NMOS1 92. The LNECT's forward voltage drop is therefore thatof a thyristor plus that of the NMOS1 92. With the increase of thecurrent, the voltage at the FOC metal strap 104, V_(m), will increase,the PMOS 100 will be turned ‘on’ and hole currents will be diverted fromthe P base through the PMOS 100 into the cathode 102. Consequently, theturn-on of the PMOS 100 will reduce the NPN transistor's current gain.If the reduction of the NPN transistor current gain, Δα_(npn) cannot becompensated by an increase of the PNP transistor current gain, Δα_(pnp)so thatα_(npn0)+α_(pnp0)−Δα_(npn)+Δα_(pnp) ≦1  (4)then the LNECT will come out of latching state. If this happens, thecurrent flowing through the PMOS 100 will tend to decrease, and so willthe V_(m). A reduced V_(m) means a reduction of the diverted currentthrough the PMOS 100 and the decrease of the Δα_(npn) hence the LNBCTenters latching again. Such negative feedback mechanism, therefore,leads to the fact that the main thyristor can only operate at thebreakover boundaries of the latching condition with the NPN transistoroperating in the active region. Under this condition, the anode 106voltage V_(A) continues to increase without significant anode currentincrease, and the increased anode voltage is supported by the mainjunction J2. and the LNECT has a high voltage current saturationcapability.

The LNECT can be turned-off by decreasing the gate electrode 108 voltageto zero or negative to turned ‘off’ the NMOS1 92, which interrupts themain current flow path, and all currents are then forced to divert tothe cathode by the PMOS 100. Moreover, both emitter switch and emittershort are used in the turn-off of the LNECT, no parasitic thyristorlimits the Reverse Bias SOA (RBSOA) of the LNECT.

Referring now to FIGS. 5A–B, there is shown a cross-sectional view ofthe another variation of the LECT (LECT-1) and its equivalent circuit,respectively. The LECT-1 has a lateral 4-layer P⁺-N-P-N⁺ thyristorstructure 2, in series with a P channel MOSFET (PMOS1) 110 integrated onthe surface of the N layer through a Floating Ohmic Contact (FOC) metalstrap 112. The FOC 112 connects the upper N⁺ emitter 114 of the PNPNthyristor and the P+ source region 116 of the PMOS1 110. The FOC 112provides the bridge for transferring emitter electron currents of theNPN transistor into hole currents, which then flow through the PMOS1 110channel and into the cathode contact 116. An N-channel depletion modeMOSFET (NMOS) 118 is also integrated at the surface of the LECT-1 whichacts as the turn-on MOSFET. A second PMOSFET (PMOS2) 120 is formedbetween the P base and the P drain of the PMOS1 110 with the P baseacting as its source. The NMOS 118 and the PMOS2 120 share the same gate122, and the gate is directly tied to the cathode contact 116, hence,the LECT-1 is a three-terminal device.

When a positive bias is applied to the anode 124 and a negative gatevoltage is applied to the gate electrode 126, the depletion mode NMOS118 will inject electrons into the n-drift region of the thyristor andtrigger the thyristor into the latching state. The latching currentflows into the N⁺ emitter of the thyristor and then flows into thecathode 116 through the FOC metal strap 112 and the series PMOS1 110.The LECT-1's forward voltage drop is therefore that of a thyristor plusthat of the PMOS1 110. With the increase of the current, the voltage atthe FOC metal strap 112, V_(m), will increase, the PMOS2 120 will beturned ‘on’ and hole currents will be diverted from the P base throughthe PMOS2 120 into the cathode 116. Consequently, the turn-on of thePMOS2 120 will reduce the NPN transistor's current gain. If thereduction of the NPN transistor current gain, Δα_(npn), cannot becompensated by an increase of the PNP transistor current gain, Δα_(pnp)so thatα_(npn0)+α_(pnp0)−Δα_(npn)+Δα_(pnp) ≦1  (5)then the LECT-1 will come out of latching state. If this happens, thecurrent flowing through the PMOS2 120 will tend to decrease, and so willthe V_(m). A reduced V_(m) means a reduction of the diverted currentthrough the PMOS2 120 and the decrease of the Δα_(pnp), hence, theLECT-1 enters latching again. Such negative feedback mechanism,therefore, leads to the fact that the main thyristor can only operate atthe breakover boundaries of the latching condition with the NPNtransistor operating in the active region. Under this condition, theanode voltage V_(A) continues to increase without significant anodecurrent increase, and the increased anode voltage is supported by themain junction J2. and the LECT-1 has a high voltage current saturationcapability.

The LECT-1 can be turned-off by increasing the gate electrode 126voltage to zero or positive to turned ‘off’ the PMOS1 110, whichinterrupts the main current flow path, and all currents are then forcedto divert to the cathode 116 by the PMOS2 120. Moreover, both emitterswitch and emitter short are used in the turn-off of the LECT-1, noparasitic thyristor limits the Reverse Bias SOA (RBSOA) of the LECT-1.

Referring now to FIGS. 6A–6B, there is shown a cross sectional view of aemitter controlled thyristor with a metal connection (ECT-MC) and itsequivalent circuit, respectively. The ECT-MC has a 4-layer P⁺-N-P-N⁺thyristor structure 2 in series with a P channel MOSFET (PMOS1) 130integrated on the top N layer through a metal strap 132. This metalstrap 132 shorting the N⁺ emitter 134 and the P⁺ region 136 which actsas the source of the PMOS1 130. And the metal strap 132 provides thebridge for transferring emitter electron currents of the upper NPNtransistor into hole currents, which then flow through the PMOS1 130channel and into the cathode contact 138. A second PMOSFET (PMOS2) 140is formed at the other side of the cathode contact 138 with the upper Pbase acting as the source. The PMOS2 140 does not have a separatecontrol gate, instead, its gate 142 is tied to the cathode contact 138.

The operation mechanism of the ECT with a metal-connection 132 issimilar as that of the ETC. During the forward current conduction, alarge negative gate voltage is applied to the main gate 144, the ECT-MCcurrent flows vertically along the PNPN thyristor structure, and thenlaterally flows through the series PMOS1 130 and into the cathode 138.The ECT-MC's forward voltage drop is therefore that of a thyristor plusthat of the PMOS1 130. With the increase of the current, the voltage ofthe metal strap 132, V_(m), will increase due to the channel resistanceof the PMOS1 130. When V_(m)>'V_(T2), where V_(T2)<0 is the thresholdvoltage of the PMOS2 140, the PMOS2 140 turns ‘on’, and hole currentswill be diverted from the upper base through the PMOS2 140 into thecathode 138. The turn-on of the PMOS2 140 will reduce the upper NPNtransistor's current gain. If the reduction of the upper NPN transistorcurrent gain, Δα_(npn), cannot be compensated by an increase of thelower PNP transistor current gain, Δ60 _(pnp) so thatα_(npn0)+α_(pnp0)−Δα_(npn)+Δα_(pnp) ≦1  (6)then the ECT-MC will come out of latching state. If this happens, thecurrent flowing through the PMOS1 130 will tend to decrease, and so willthe V_(m). A reduced V_(m) means a reduction of the diverted currentthrough the PMOS2 140 and the decrease of the Δα_(npn) hence the ECT-MCenters latching again. Such negative feedback mechanism, therefore,leads to the fact that the main thyristor can only operate at thebreakover boundaries of the latching condition with the NPN transistoroperating in the active region. Under this condition, the anode voltageV_(A) continues to increase without significant anode 146 currentincrease, and the increased anode voltage is supported by the mainjunction J3. The lower PNP transistor (also operating in the activeregion) supplies base current for the upper NPN transistor, and thesaturation current is the holding current of the thyristor with bothPMOS1 130 and PMOS2 140 conducting. At very high voltages, the increaseof Δα_(pnp) will compensate Δα_(npn), and the ECT-MC will tend to latchagain until equation (6) is violated. The violation point can beconsidered to correspond to the ECT-MC's FBSOA boundary point.

The ECT-MC can be turned-off by increasing the gate electrode voltage tozero or positive value in the PMOS1 130, which interrupts the maincurrent flow path. All currents are then forced to divert to the cathodeby the PMOS2 140. Both emitter switch (PMOS1) 130 and emitter short(PMOS2) 140 are used in the turn-off of the ECT-MC, and unlike in theEST, no parasitic thyristor limits the RBSOA of the ECT-MC.

Referring now to FIGS. 7A–B, there is shown a cross-sectional view ofthe Single Gate NMOS ECT (SNECT) and its equivalent circuit,respectively. The SNECT has a 4-layer PNPN thyristor structure 2 inseries with a N channel MOSFET (NMOS 1) 150 integrated on the top of theP well through a Floating Ohmic Contact (FOC) metal strap 152. The FOC152 connects the upper N+ emitter 154 of the PNPN thyristor and the N+drain region 156 of the NMOS 1. An N-channel depletion mode MOSFET(NMOS2) 162 is also integrated at the surface of the SNECT which acts asthe turn-on MOSFET. A P-channel MOSFET (PMOS) 160 is formed between twoP regions. The NMOS2 162 and the PMOS 160 share the same gate 164, andthe gate is directly tied to the cathode contact 166; hence, the SNECTis a three-terminal device.

When a positive bias is applied to the anode 168 and a positive gatevoltage is applied to the gate electrode 170, the depletion mode NMOS1150 will inject electrons into the n-drift region of the thyristor andtrigger the thyristor into the latching state. The latching currentflows into the upper N emitter 172 of the thyristor and then flowslaterally into the cathode through the FOC metal strap 152 and theseries NMOS1 150. The SNECT's forward voltage drop is therefore that ofa thyristor plus that of the PMOS 160. With the increase of the current,the voltage at the FOC metal strap 152, V_(m), will increase, the PMOS160 will be turned ‘on’ and hole currents will be diverted from theupper base of the NPN transistor through the PMOS 160 into the cathode166. Consequently, the turn-on of the PMOS 160 will reduce the upper NPNtransistor's current gain. If the reduction of the upper NPN transistorcurrent gain, Δα_(pnp), cannot be compensated by an increase of thelower PNP transistor current gain, Δα_(npn), so thatα_(npn0)+α_(pnp0)−Δα_(npn)+Δα_(pnp) ≦1  (7)then the SNECT will come out of latching state. If this happens, thecurrent flowing through the PMOS 160 will tend to decrease, and so willthe V_(m). A reduced V_(m) means a reduction of the diverted currentthrough the PMOS 160 and the decrease of the Δα_(npn) hence, the SNECTenters latching again. Such negative feedback mechanism, therefore,leads to the fact that the main thyristor can only operate at thebreakover boundaries of the latching condition with the NPN transistoroperating in the active region. Under this condition, the anode voltageVA continues to increase without significant anode current increase, andthe increased anode voltage is supported by the main junction J2. andthe SNECT has a high voltage current saturation capability.

The SNECT can be turned-off by decreasing the gate electrode 170 voltageto zero or negative to turned ‘off’ the NMOS1 150, which interrupts themain current flow path, and all currents are then forced to divert tothe cathode 166 by the PMOS 160. Moreover, both emitter switch andemitter short are used in the turn-off of the SNECT, no parasiticthyristor limits the Reverse Bias SOA (RBSOA) of the SNECT.

Referring now to FIGS. 8A–B, there is shown a cross-sectional view of asingle gate emitter controlled thyristor SECT and its circuitequivalent, respectively. The SECT has a 4-layer PNPN thyristorstructure 2 in series with a P channel MOSFET (PMOS1) 180 integrated onthe surface of the N substrate through a Floating Ohmic Contact (FOC)metal strap 182. The FOC 182 connects the upper N+ emitter 184 of thePNPN thyristor and the P source region 186 of the PMOS1 180. The FOC 182provides the bridge for transferring emitter electron currents of theupper NPN transistor into hole currents, which then flow through thePMOS1 180 channel and into the cathode contact. An N-channel depletionmode MOSFET (NMOS) 188 is also integrated at the surface of the SECTwhich acts as the turn-on MOSFET. A second PMOSFET (PMOS2) 190 is formedbetween the turn-on NMOS 188 and the PMOS1 180 with the upper P baseacting as its source. The NMOS 188 and the PMOS2 190 share the samegate, and the gate is directly tied to the cathode contact 192, hence,the SECT is a three-terminal device.

When a positive bias is applied to the anode 194 and a negative gatevoltage is applied to the gate electrode 196, the depletion mode NMOSwill inject electrons into the n-drift region of the thyristor andtrigger the thyristor into the latching state. The latching currentflows into the upper N emitter of the thyristor and then flows laterallyinto the cathode through the FOC metal strap 182 and the series PMOS1180. The SECT's forward voltage drop is therefore that of a thyristorplus that of the PMOS1 180. With the increase of the current, thevoltage at the FOC metal strap 182, V_(m), will increase, the PMOS2 190will be turned ‘on’ and hole currents will be diverted from the upperbase through the PMOS2 190 into the cathode 192. Consequently, theturn-on of the PMOS2 190 will reduce the upper NPN transistor's currentgain. If the reduction of the upper NPN transistor current gain,Δα_(npn) cannot be compensated by an increase of the lower PNPtransistor current gain, Δα_(pnp), so thatα_(npn0)+α_(pnp0)−Δα_(npn)+Δα_(pnp) ≦1  (8)then the SECT will come out of latching state. If this happens, thecurrent flowing through the PMOS2 190 will tend to decrease, and so willthe V_(m). A reduced V_(m) means a reduction of the diverted currentthrough the PMOS2 190 and the decrease of the Δα_(npn) hence the SECTenters latching again. Such negative feedback mechanism, therefore,leads to the fact that the main thyristor can only operate at thebreakover boundaries of the latching condition with the NPN transistoroperating in the active region. Under this condition, the anode voltageV_(A) continues to increase without significant anode current increase,and the increased anode voltage is supported by the main junction J2.and the SECT has a high voltage current saturation capability.

The SECT can be turned-off by increasing the gate electrode voltage tozero or positive to turned ‘off’ the PMOS1 180, which interrupts themain current flow path, and all currents are then forced to divert tothe cathode 182 by the PMOS2 190. Moreover, both emitter switch andemitter short are used in the turn-off of the SECT, no parasiticthyristor limits the Reverse Bias SOA (RBSOA) of the SECT.

Referring now to FIGS. 9A and 9B there is shown a cross-sectional viewof an emitter turn off thyristor (ETO) and its equivalent circuit,respectively. The ETO comprises a PNPN thyristor 202 and an emitterswitch 200. MOSFETs or other MOS gated devices are used to build theemitter switch 200. The thyristor 202 can be a GTO or SCR device. Thespecially selected MOS gated device have their minimum forward voltageat high current. To turn off the thyristor 202, simply turn-off theemitter-devices by dropping the voltage at the gate 204 to zero. Asshown by the arrows, in order to turn the thyristor on, the MOS switch200 turns on and the thyristor gate injects current. In order to turnthe thyristor off, MOS switch 204 is turned off and the thyristor gate Bdrains current.

Referring now to FIGS. 10A and B there is shown a cross-sectional viewof an improved emitter turn off thyristor (ETO) and its equivalentcircuit, respectively. The circuit is similar to the one shown in FIGS.9A–B with the addition of a diode 206 connected between the thyristorgate B and the cathode terminal. The threshold voltage of the diode 206selected is higher than the voltage drop across the thyristor gate tocathode plus the voltage of the emitter-switch 200 in an on-state. Whenthe thyristor 202 is going to be turned on or in on state, the thyristorgate B voltage is always lower than that of the gate switch's 204threshold voltage, the gate-switch 204 acts as open circuit. During theturn-off transient process, the emitter-switch 200 is off and can notconduct current. The diode 206 provides a path for the anode current toflow at turn-off and terminal B can be an open circuit.

Referring now to FIGS. 11A and 11B, there is shown a cross-sectionalview of an emitter turn off thyristor (ETO) and its equivalent circuit.The circuit is similar to that shown in FIGS. 10A–B with the addition ofa capacitor 210 connected in parallel to the diode 206. The capacitor210 is used to help turn on the thyristor 202 by providing analternative turn-on current for the thyristor gate B as shown by thearrow 214. The voltage of the capacitor 210 is clamped to the thresholdvoltage of the diode 206. To turn-on the ETO, the emitter-switch 200 isturned on and the capacitor 210 discharges through the thyristorsgate-cathode and emitter-switch path. The discharge current acts as theturn on current for the thyristor 202. The capacitor 210 is chargedduring the turn-off transient when the anode current flows out of thethyristor gate B as shown by the arrow 216. With the structure describeabove, the thyristor 202 is fully a MOS controlled device. It is turnedon by adding a voltage on the MOS emitter-switch MOS gate 212. It isturned off by removing that voltage.

Referring now to FIGS. 12A and 12B there is shown a cross-sectional viewof an improved emitter turn off thyristor (ETO) and its circuitequivalent, respectively. This circuit is similar to the one describedwith reference to FIGS. 11A–B, above, with the diode 206 being replacedwith a Zener diode 220. Zener diodes are easier to achieve higherturn-on voltage than a diode; hence more energy can be stored. To turnon the thyristor, the MOS emitter switch 200 is turned on and thecapacitor 210 injects current into the thyristor gate B as shown byarrow 214. For turn-off, the MOS emitter switch 200 is turned off andthe Zener diode 220 drains current to charge the capacitor 210 as shownby arrow 216.

Referring now to FIGS. 13A and 13B there is shown a cross-sectional viewof an emitter turn off thyristor (ETO) and its equivalent circuit,respectively. In this structure, two N-channel MOSFETs 200 and 224, onefor the emitter switch and one for the gate switch, are used. The NMOS224 has its drain and gate terminals connected together and canfunctions as the Zener diode discussed above but can handle highercurrents. As before, for to turn on the thyristor, the MOS emitterswitch 200 is turned on and the capacitor 210 injects current into thethyristor gate B as shown by arrow 214. For turn-off, the MOS emitterswitch 200 is turned off the NMOS 224 drains current to charge thecapacitor 210 as shown by arrow 216.

Referring now to FIGS. 14A and 14B, there is shown an emitter turn offthyristor (ETO) and its equivalent. This circuit is similar to thecircuit shown above with reference to FIGS. 13A–B excepts the NMOStransistors are replaced with PMOS transistors 234 and 236. The PMOS 236has its gate and drain terminals tied together. Compared to that of NMOStransistors, the PMOS transistors 234 and 236 drain is connecteddirectly to the cathode terminal.

Referring now to FIGS. 15A and 15B there is shown a cross-sectional viewof an emitter turn-off thyristor that attach a MOSFET die on a singleemitter finger of the thyristor or GTO, and its equivalent circuit,respectively. To realize this ETO thyristor, the emitter-switch alongwith the gate-switch is packaged along with a gate-turn off thyristor.(GTO) 302. As shown, an N-MOSFET die 300, acting as the emitter switch,is mounted on the cathode K of the GTO's die 302. The drain 304 of theNMOS device contacts directly with the cathode 306 of the GTO 302 with ametal strip 308. The source of the NMOS device becomes the cathode K ofthe ETO. By mounting the emitter-switch onto the GTO in the die form,the size of the ETO is minimized. Further, stray inductance betweentheir connection is minimized.

Referring now to FIGS. 16A and 16B there is shown a cross-sectional viewof an ETO that attaches a multiple die form MOSFET on multiple emitterfingers and its circuit equivalent, respectively. In this structure,both the N-MOS devices 300 and the GTO 302 are in die form. They do notcontact each other directly but with a metal strip 308 between them. Themetal strip 308 is put on the GTO's cathode, covering several cathode(emitter) fingers 310. In this form, the dimension of the GTO's cathodefinger is not critical for the die form mounting. The cathode finger 310can be as thin as possible and the MOS die can be as large as possible.On the other hand, the metal strip 308 supplies a path for horizontalcurrent. So the MOS die is not needed to cover the whole GTO's cathode.Their number is only determined by the current capability but not theirsize.

Referring now to FIGS. 17A–D there is shown various views of a schematicE fabrication package. In this structure, all the components are used intheir packaged forms. The packaged GTO 400 is put in the center of around metal layer (copper layer 2) 403 which contacts the GTO's cathode.An N-MOSFET Q1 used to build the emitter-switch is put on the metallayer around the GTO 400, and a P-MOSFET Q2 is also put on the metallayer 403 around the GTO 400. In the preferred embodiment, Q1 comprisesa plurality of N-MOSFETs connected in parallel around the GTO 400. Thevarious connections can be made on board 406. Similarly, the emitterswitch Q2 may comprise a plurality P-MOSFETs connected in parallelaround the GTO 400. In addition, the emitter switch Q2 is not limited toP-MOSFETS, but may be any switching mechanism such as those described inFIGS. 9–14. Another metal layer (copper layer 3) 403 is put on thesecond metal layer 402 and acts as the ETO cathode. An insulation layer405 electrically insulates the metal layers, 402 and 403. A top metallayer (copper layer 1) 401 is put on the anode of the GTO 400 andfasteners such as clamps or screws 404 are used to hold the structuretogether. Alternately, the device may simply be soldered together. Thetop metal layer 401 provides an additional means for dissipating heatbut is not necessary for operation of the device. A positive voltageapplied to the gate of the G1 of the first N-MOSFET Q1, and a currentinjected to terminal B turns the thyristor 400 on causing a current toflow between said anode and cathode terminals. A zero to negativevoltage applied to the gate of Q1 turns the thyristor device to an offstate stopping the current flow. During the turn-off, the cathodecurrent is interrupted and is forced to transfer to the gate path,passing through the gate switch Q2 connected as a Zener diode. The ETOimplemented this way is a four terminal device, providing MOS turn-off,and conventional turn-on through terminal B. Because the thyristor issandwiched between metal plates, it has double side cooling for superiorheat dissipation. In addition, since the GTO control devices Q1 and Q2are arranged in a circular path around the GTO 400, the parasiticinductance in the current path between the anode and cathode is greatlyreduced. Q1 and Q2 may be arranged in a single circle around the GTO 400or may be arranged in two or more concentric circles around the GTO 400.

FIG. 17E shows the turn-on timing diagram for the ETO package whereinthe voltage drop across the anode and cathode drops from 2000V to near0V in about 6 μs and the current conducted between the anode and cathodegoes from 0 A to about 1000 A in 25 μs. Similarly, FIG. 17F shows theturn-off timing diagram for the ETO package wherein the current flowbetween the anode and cathode is turned off in about 2 μs.

Referring now to FIG. 18, there is shown a different kind of connectionthat can be implemented in the ETO. By adding several components, athree terminal device can be obtained where both the turn-on andturn-off is controlled by one single gate, G. A negative feedbacknetwork, 500, is also implemented to control the maximum voltage onemitter switch Q1 during the turn-off of that switch. An optionalcapacitance C 600, is in parallel with gate switch Q2 to provideadditional turn-on current. This cap is able to deliver additionalturn-on current because it will store energy in a previous turn-offtransient. The amount of energy is proportional to the square of thevoltage on the gate switch Q2 that acts like a Zener diode, This ETOturns on when a positive voltage is added to gate and it turns off whenthat voltage is reduced to zero or negative.

Referring flow to FIG. 19, this circuit can also be implemented in theETO and is similar to that shown in FIG. 18. The difference is that aseparate control is added to gate switch Q2. The advantage of adding acontrol is that instead of having the gate switch Q2 operating like aZener diode, hence very high power dissipation, the gate switch Q2 canoperate in its linear region to reduce the impedance and thermaldissipation. The gate switch Q2 is only needed to be ‘on’ during theinitial stage of the device turn-off when a very high anode to gateCurrent exists. After the passing of that high anode-to-gate current,gate switch Q2 can be turned off, allowing the anode to gate tailcurrent to charge the capacitor.

While the invention has been described in terms of preferredembodiments, those skilled in the art will recognize that the inventioncan be practiced with modification within the spirit and scope of theappended claims.

1. A thyristor device package having a cathode terminal and an anodeterminal, comprising: a thyristor device having a thyristor emitter, athyristor collector, and a thyristor gate, said thyristor comprisingalternating P-type and N-type semiconductor regions; a first discretemetal oxide semiconductor (MOS) transistor connected in series with saidthyristor between said cathode terminal and said thyristor emitter; asecond discrete MOS transistor connected between said cathode terminaland said thyristor gate; and means for injecting current into saidthyristor gate for triggering said thyristor into a latching state;wherein a first voltage applied to a gate terminal of said first MOStransistor causes a current to flow between said cathode terminal andsaid anode terminal turning said thyristor device package to an onstate, and a zero to second voltage applied to said gate of said firstMOS transistor turns said thyristor device package to an off state.
 2. Athyristor device package as recited in claim 1 further comprising afloating ohmic contact (FOC) for shorting said emitter and a sourceterminal of said first MOS transistor.
 3. A thyristor device package asrecited in claim 1 further comprising a metal strap for shorting saidthyristor emitter and a source terminal of said first MOS transistor. 4.A thyristor device package as recited in claim 1, wherein a gateterminal of said second MOS transistor is connected to said cathodeterminal.
 5. A thyristor device package comprising: a first metal plate;a second metal plate; a third metal plate electrically insulated fromsaid second metal plate; a thyristor sandwiched between said first metalplate and said second metal plate, a collector of said thyristorcontacting said first metal plate acting as an anode for said thyristordevice package; a first discrete metal oxide semiconductor (MOS)transistor positioned on said second metal plate adjacent saidthyristor, said first MOS transistor having a first terminal connectedto an emitter of said thyristor and a second terminal connected to saidthird metal plate acting as a cathode for said thyristor device package;and a second discrete MOS transistor positioned on said second metalplate adjacent said thyristor, said second MOS transistor having a firstterminal connected to a gate of said thyristor, said second MOStransistor further having a second terminal connected to said thirdmetal plate, wherein a first voltage applied to a gate terminal of saidfirst MOS transistor turns said thyristor to an on state causing acurrent to flow between said cathode and said anode, and a zero tosecond voltage applied to said gate of said first MOS transistor turnssaid thyristor device to an off state.
 6. A thyristor device package asrecited in claim 5, further comprising a clamp means for holding saidfirst, second and third metal plates together.
 7. A thyristor devicepackage as recited in claim 5, wherein said first, second and thirdmetal plates comprise copper plates.
 8. A thyristor device package asrecited in claim 5, wherein said first MOS transistor and said secondMOS transistor are complementary.
 9. A thyristor device package asrecited in claim 5, wherein said second discrete MOS transistor furtherincludes a gate terminal connected to said third metal plate.
 10. Athyristor device package comprising: a gate turn-off (GTO) thyristorcomprising a thyristor gate, a thyristor emitter, and a thyristorcollector forming an anode terminal; a first plurality of discreteswitching devices connected in parallel and arranged in a circularfashion around said GTO thyristor, a first terminal of respective onesof said first plurality of discrete switching devices connected to saidthyristor emitter and a second terminal of respective ones of said firstplurality of discrete switching devices connected to a cathode terminalof said thyristor device package; and a second plurality of discreteswitching devices connected in parallel and arranged in a circularfashion around said GTO thyristor, a first terminal of respective onesof said second plurality of discrete switching devices connected to saidthyristor gate and a second terminal of respective ones of said secondplurality of discrete switching devices connected to said cathodeterminal of said thyristor device package, wherein a first voltageapplied to gate terminals of said first plurality of discrete switchingdevices turns said GTO thyristor to an on state causing a current toflow between said cathode terminal and said anode terminal, and a zeroto second voltage applied to said gate terminals of said first pluralityof discrete switching devices turns said GTO thyristor to an off state.11. A thyristor device package as recited in claim 10, furthercomprising: a first metal plate forming said cathode terminal; a secondmetal plate separated from said first metal plate by an insulationlayer, wherein said GTO thyristor and said discrete switching devices ofsaid first and second pluralities of discrete switching devices arepositioned on said second metal plate, said first and second metalplates acting as a heat sink.
 12. A thyristor device package as recitedin claim 10 further comprising a third metal plate forming said anodeterminal of said thyristor device package.
 13. A thyristor devicepackage as recited in claim 10 wherein said discrete switching devicesof said second plurality of discrete switching devices comprise a diode.14. A thyristor device package as recited in claim 10 wherein saiddiscrete switching devices of said second plurality of discreteswitching devices comprise a diode connected in parallel with acapacitor.
 15. A thyristor device package as recited in claim 10 whereinsaid discrete switching devices of said second plurality of discreteswitching devices comprise a Zener diode connected in parallel with acapacitor.
 16. A thyristor device package as recited in claim 10 whereinsaid discrete switching devices of said second plurality of discreteswitching devices comprise a transistor connected in parallel with acapacitor.
 17. A thyristor device package including a thyristor elementhaving an anode terminal, an emitter terminal and a gate terminal, afirst discrete semiconductor switch connected in series with saidemitter terminal of said thyristor element by a first terminal of saidfirst discrete semiconductor switch, a second discrete semiconductorswitch connected in series with said gate terminal of said thyristorelement by a first terminal of said second discrete semiconductorswitch; second terminals of said first and second discrete semiconductorswitches being connected together, and means for shorting said emitterterminal of said thyristor element to said first a terminal of saidfirst discrete semiconductor switch or for injecting current into saidgate terminal for triggering said thyristor into a latching state;wherein said first and second discrete semiconductor switches arearranged such that a signal of a first type applied to said firstdiscrete semiconductor switch turns said thyristor element to anon-state and a signal of a second type applied to said firstsemiconductor switch turns said thyristor element to an off-state, andwherein at least one of said first and second semiconductor switches isconstituted by a plurality of semiconductor devices.